datasheet pll building block ICS663 idt? / ics? pll building block 1 ICS663 rev e 012006 description the ICS663 is a low cost phase-locked loop (pll) designed for clock synthesis and synchronization. included on the chip are the phase detector, charge pump, voltage controlled oscillator (vco) and an output buffer. through the use of external reference and vco dividers (implemented with the ics674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. the phase detector and vco functions of the device can also be used independently. this enables the configuration of other pll circuits. for example, the ICS663 phase detector can be used to control a vcxo circuit such as the mk3754. for applications requiring power down or output enable features, please refer to the ics673-01. features ? packaged in 8-pin soic (pb free) ? output clock range 1 mhz to 100 mhz (3.3 v), 1 mhz to 120 mhz (5 v) ? external pll loop filter enables configuration for a wide range of input frequencies ? ability to accept an input cl ock in the khz range (video hsync, for example) ? 25 ma output drive c apability at ttl levels ? lower power cmos process ? +3.3 v 5% or +5 v 10% operating voltage ? used along with the ics674-01, forms a complete pll circuit ? phase detector and vco blocks can be used independently for other pll configurations ? industrial temperature version available ? for better jitter performance, use the mk1575 block diagram refin phase/ frequency detector vco 4 2 sel lfr lf up fbin down i cp i cp clk vdd mux 1 0 external feedback divider (such as the ics674-01) clock input
ICS663 pll building block pll building block idt? / ics? pll building block 2 ICS663 rev e 012006 pin assignment vco post divide select table 0 = connect pin directly to ground 1 = connect pin directly to vdd pin descriptions 1 2 3 fbin 4 vdd gnd clk lf sel lfr 8 7 6 5 refin 8 pin (150 mil) soic sel vco post divide 08 12 pin number pin name pin type pin description 1 fbin input feedback clock input. connect the output of the feedback divider to this pin. falling edge triggered. 2 vdd power vdd. connect to +3.3 v or +5 v. 3 gnd power connect to ground. 4 lf input loop filter connection (refer to figure 1 on page 5). when using the phase detector block only, this pin serves as the charge pump output. when using the vco block only, this pin serves as vco input control voltage. 5 lfr input loop filter return (refer to figure 1 on page 5). 6 sel input select pin for vco post divide, as per above table. 7 clk output clock output. 8 refin input reference clock input. connect the input cl ock to this pin. falling edge triggered.
ICS663 pll building block pll building block idt? / ics? pll building block 3 ICS663 rev e 012006 absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the ICS663. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 5% or 5.0 v 10%, ambient temperature -40 to +85 c, unless stated otherwise item rating supply voltage, vdd 7v all inputs and outputs -0.5v to vdd+0.5v ambient operating temperature 0 to +70 c industrial temperature -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.13 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.13 5.5 v logic input high voltage v ih refin, fbin, sel 2v logic input low voltage v il refin, fbin, sel 0.8 v lf input voltage range v i 0vddv output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v output high voltage, cmos level v oh i oh = -8 ma vdd-0.4 operating supply current idd vdd = 5.0 v, no load, 40 mhz 15 ma short circuit current i os clk 100 ma input capacitance c i sel 5 pf
ICS663 pll building block pll building block idt? / ics? pll building block 4 ICS663 rev e 012006 ac electrical characteristics vdd = 3.3 v 5%, ambient temperature -40 to +85 c, unless stated otherwise vdd = 5.0 v 10%, ambient temperature -40 to +85 c, unless stated otherwise note 1: minimum input frequency is limited by loop filter design. 1 khz is a practical minimum limit. thermal characteristics parameter symbol conditions min. typ. max. units output clock frequency (from pin clk) f clk sel = 1 1 100 mhz sel = 0 0.25 25 mhz input clock frequency (into pins refin or fbin) f ref note 1 8 mhz output rise time t or 0.8 to 2.0v 1.2 2 ns output fall time t of 2.0 to 0.8v 0.75 1.5 ns output clock duty cycle t dc at vdd/2 40 50 60 % jitter, absolute peak-to-peak t j 250 ps vco gain k o 200 mhz/v charge pump current i cp 2.5 a parameter symbol conditions min. typ. max. units output clock frequency (from pin clk) f clk sel = 1 1 120 mhz sel = 0 0.25 30 mhz input clock frequency (into pins refin or fbin) f ref note 1 8 mhz output rise time t or 0.8 to 2.0 v 0.5 1 ns output fall time t of 2.0 to 0.8 v 0.5 1 ns output clock duty cycle t dc at vdd/2 45 50 55 % jitter, absolute peak-to-peak t j 150 ps vco gain k o 200 mhz/v charge pump current i cp 2.5 a parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
ICS663 pll building block pll building block idt? / ics? pll building block 5 ICS663 rev e 012006 external components the ICS663 requires a minimum number of external components for proper operation. a decoupling capacitor of 0.01 f should be connected between vdd and gnd as close to the ICS663 as possible. a series termination resistor of 33 ? may be used at the clock output. special considerations must be made in choosing loop components c 1 and c 2 : 1) the loop capacitors should be a low-leakage type to avoid leakage-induced phase noise. for this reason, do not use any type of polarized or electrolytic capacitors. 2) microphonics (mechanical board vibration) can also induce output phase noise when the loop bandwidth is less than 1 khz. for this reason, ceramic capacitors should have c0g or np0 dielectric. avoid hi gh-k dielectrics like z5u and x7r. these and some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with vcxo operation. for larger loop capacitor values such as 0.1 f or 1 f, pps film types made by panasonic, or metal poly types made by murata or cornell du bilier are re commended. for questions or changes regarding loop filter characteristics, please contact your sales area fae, or idt applications. avoiding pll lockup in some applications, the ICS663 can ?lock up? at the maximum vco frequency. the way to avoid this problem is to use an external divider that always operates correctly regardless of the clk output frequency. the clk output frequency may be up to 2x the maximum output clock frequency listed in the ac electrical characteristics above when the device is in an unlocked condition. make sure that the external divider can operate up to this frequency. explanation of operation the ICS663 is a pll building block circuit that includes an integrated vco with a wide operating range. the device uses external pll loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 khz hsync input. the phase/frequency detector compares the falling edges of the clocks inputted to fbin and refin. it then generates an error signal to the charge pump, which produces a charge proportional to this error. the external loop filter integrates this charge, producing a voltage that then controls the frequency of the vco. this process continues until the edges of fbin are aligned with the edges of the refin clock, at which point the out put frequency will be locked to the input frequency. figure 1. example configuration -- generating a 20 mhz clock from a 200 khz reference refin +3.3 or 5 v vdd sel 0.01 f fbin 200 khz 100 digital divider such as ics674-01 gnd clk lfr 20 mhz lf c 1 r z c 2 200 khz ICS663
ICS663 pll building block pll building block idt? / ics? pll building block 6 ICS663 rev e 012006 determining the loop filter values the loop filter components consist of c 1 , c 2 , and r z . calculating these values is best illustrated by an example. using the example in figure 1, we can synthesize 20 mhz from a 200 khz input. the phase locked loop may be approximately described by the following equations: bandwidth damping factor, where: k o = vco gain (mhz/volt) i cp = charge pump current ( a) n = total feedback divide from vco, including the internal vco post divider c 1 = loop filter capacitor (farads) r z = loop filter resistor (ohms) as a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e., in this example, using the above equation, bandwidth should be less than or equal to 10 khz. by setting the bandwith to 10khz and using the first equation, r z can be determined since all other variables are known. in the example of figure 1, n = 200, comprising the divide by 2 on the chip (vco post divider) and the external divide by 100. therefore, the bandwidth equation becomes: and r z = 25 k ? choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes: and c 1 = 1.25 nf (1.2 nf is the nearest standard value). the capacitor c 2 is used to damp transients from the charge pump and should be approximately 1/20th the size of c 1 , i.e., therefore, c 2 = 60 pf (56 pf nearest standard value). to summarize, the loop filter components are: c 1 = 1.2 nf c 2 = 56 pf r z = 25 k ? r z k o i cp ?? ( ) 2 n ? ---------------------- ----------------- -- - = ?? n ----------------- ----------------- -- = bw refin () 20 ? 0,000 r z 200 2. 5 ?? 2 200 ? ------------------- ---------------- -- - = . 7 25 000 , 2 ------------------- 200 2.5 c ?? 200 ------------------ ----------------- - = c 2 c 1 2 0 ? ?
ICS663 pll building block pll building block idt? / ics? pll building block 7 ICS663 rev e 012006 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 663mlf 663mlf tubes 8-pin soic 0 to +70 c 663mlft 663mlf tape and reel 8-pin soic 0 to +70 c 663milf 663milf tubes 8-pin soic -40 to +85 c 663milft 663milf tape and reel 8-pin soic -40 to +85 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
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